Memory devices, in particular first-in first-out (FIFO) buffers, typically employ a variety of status flags including empty, full, half-full, almost full, almost empty and cascade. The various flags indicate when certain conditions are met. During the testing of such a device, the various flags make it more difficult to provide thorough, fine grained, testing of the device. In particular, with increased density designs in order to fully simulate the schematic database of the device, the entire depth of the device must be accessed and tested. In the case where the device has a status flag that activates at one particular end of the device exclusively, the entire depth of the device must be written to and/or read before a single occurrence of a particular flag is realized. There are numerous tests that need to be performed at each status flag or boundary. However, thousands of "dummy" cycles are needed to place the device into the desired condition for a single execution of the status flag. The following TABLE 1 illustrates a number of typical FIFO depths as well as status flag/boundary flag conditions:
TABLE 1 ______________________________________ Depths Status Flags/Boundary ______________________________________ 256, 512, 1K, 2K, 4K Empty, Full, Half Full, Casdade 64, 256, 512, 1K, 2K, 4K, 8K Empty, Full, Half Full, Cascade, Programmable Almost Full/Empty 64, 256, 512, 1K, 2K, 4K Empty, Full, Half Full, Cascade, Programmable Almost Full/Empty 512, 1K, 2K, 4K Empty, Full, Half Full, Cascade, Programmable Almost Full/Empty 256, 512, 1K, 2K Empty, Full, Half Full, Cascade, Programmable Almost Full/Empty ______________________________________
As can be seen from TABLE 1, even the smallest depth for certain device families will require numerous "dummy" cycles to be executed before reaching the desired boundary condition.
FIG. 1 illustrates a previous approach for configuring the device depth of a particular device by a combination of metal options and bond options. The device 10 generally comprises a size decoder block 12, a write counter 14, a read counter 16 and a status flag logic block 18. The size decoder 12 has an input 20 and an input 22 that generally receive bond options information. The size decoder block 12 presents information on a size bus 24 that is presented to an input 26 of the status flag logic block 18. The size bus 24 presents a signal on a data bus 28 that is received at an input 30 of the write counter 14. The write counter 14 also has an input 32 that receives a write clock signal WCLK. The write counter 14 presents a signal at an output 34 that is received at an input 36 of the status flag logic block 18. The size bus 24 presents a signal on a data bus 38 that is received at an input 40 of the read counter 16. The read counter 16 also has an input 42 that receives a read clock signal RCLK. The read counter 16 presents a signal at an output 44 that is received at an input 46 of the status flag logic block 18.
The width of the size bus 24 is determined by all the possible depth combinations allowed by the size decoder block 12. For example, a device with several metal options defining several families of devices (e.g., .times.9, .times.18, etc.) having various bond options defines the required device depth of the size bus 24. As a result, two bond options would provide four depths per metal option.